1. Technical Field
This invention relates to electronic imaging devices and, in particular, to imagers having FET reset switches.
2. Related Art
Conventionally, CMOS imagers contain a number of photodiodes that are continuously queried and reset. The resetting of the photodiodes attempts to place each of the photodiodes into a known state (i.e. an expected voltage or charge level) and is commonly controlled by a N-channel Metal Oxide Semiconductor (NMOS) Field Effect Transistor (FET) acting as a reset switch. The NMOS FET has a drain implant that is in direct contact with a lighter doped P-well and protrudes into the material under the gate region of the NMOS FET.
The utilization of NMOS FETs acting as reset switches in CMOS imagers results in an additional source of noise, commonly known as reset noise (known as kTC noise). The typical construction of a NMOS FET allows charge to flow back to the drain and contributes to the reset noise in a CMOS imager. The length of time between resets and temperature changes affects the rate at which charge in a NMOS FET flows back to the drain and increases the reset noise when voltage is removed from the gate. The problem created by reset noise in a CMOS imager is that it causes uncertainty bout the voltage values at the photodiodes after a reset. Attempts to compensate for reset noise in a NMOS FET have been generally unsuccessful due to charge redistribution that depends on the localized substrate noise (i.e. correlated double sampling measurements of the reset noise during a read operation). In addition, for signal readout circuits configured to integrate the photogenerated signal on the total sense capacitance, such as the source follower arrangement of Fry, et al., (IEEE JSSC, Vol. SC-5, No. 5, October 1970), is affected by the increased capacitance. The increased capacitance of a conventional reset FET decreases the electrical gain of the signal readout circuits. The decreased electrical gain results from the sense capacitance being the aggregate of the detector capacitance and various stray capacitances in compact pixel designs. The stray capacitances include, for example, the gate capacitance of the transistor gate driven by the photodiode cathode and the associated capacitance of the reset transistor. Therefore, the increased capacitance of a conventional NMOS FET reset switch results in optical degraded sensitivity for the CMOS imager due to both higher reset noise and lower electro-optical sensitivity. Thus, the use of known types of compensation for reset noise still results in a loss of sensitivity in the CMOS imager.
Additional reset noise problems occur due to the single chip construction of a conventional NMOS FET utilized as a reset switch in a CMOS imager. Construction of conventional NMOS FET utilize fabrication methods using sub-micron technology. As a result, the NMOS FET is susceptible to junction leakage. It is not uncommon for high leakage to occur from the increased electric field associated with a shallow junction, Arsenic implant damage, gate induced drain leakage, or a combination of all of the previous. The junction leakage of a conventional NMOS FET results in poor optimization and continuous soft resets during low light operation of a CMOS imager. Soft resets generate image lag because the charge that is not fully cleared from the photo-detector is subsequently added to the signal in the next integration period. The poor optimization and continuous soft resets significantly contributes to the reset noise and loss of sensitivity at low light level problems in a CMOS imager. Therefore, there is a need for a device and method to increase sensitivity at low light level while reducing the reset noise in CMOS imagers regardless of temperature and periods between resets of photodiodes while reducing junction leakage of the NMOS FET.
The tapered threshold reset FET for a CMOS imager has a sensor having a transistor with a gate located partially over a source and partially over a drain having material between the source and drain beneath the gate of a predetermined length. The sensor also has a detection device that may be coupled to the drain by a signal path, where the material allows the detection device to be reset to a predetermined state.
Broadly conceptualized, the sensor may be formed with a reset transistor that reduces the capacitance of the photodiode. This may be accomplished by moving the p-type well, that isolates the source from the drain such that the p-type well partially dopes the channel of the transistor. The transistor may also be constructed to reduce reset noise through the use of the tapered reset operation. The tapered reset operation may include a reset transistor of relatively high impedance capable of suppressing the basic reset noise associated with the photodiode capacitance via an on-chip circuit and by using a channel implant that increases the reset voltage level for creating the reset channel.
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.